VHDL Codes for FPGA implementation
- Full Adder (1-bit)
- Full Adder (4-bit)
- 7-Segment Decoder (3-8)
- 4-bit ALU
- Comparator (4-bit)
- Multiplexer (8 X 1)
- Demultiplexer (1 X 8)
- Binary to Gray Code Conversion
- (Even) Parity Generator
- D Flip Flop
- T flip-flop
- Binary Coded Decimal Adder(1 bit)
- MULTIPLIER(2 bits)
- Decoder(3-8)
- Encoder(0-9)
- In Viva you have to implement and run a full program (obtained by card picking).
Complete Source Codes, with UCF file and circuit diagram are provided here:
